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31109 ms/61202rm (ot)/62599rm (ki) no.6201-1/12 http://onsemi.com semiconductor components industries, llc, 2013 may, 2013 lb1876 overview the lb1876 is a driver for polygon mirror motors such as used in laser printers and similar equipment. it incorporates all necessary circuitry (speed control + driv er) on a single chip. direct pwm drive enables drive with low power loss. features ? 3-phase bipolar drive ? direct pwm drive technique ? built-in lower side output diode ? output current limiter ? reference clock input circuit (fg frequency equivalent) ? pll speed control circuit ? phase lock detector output (with masking function) ? built-in protection circuitry includes cu rrent limiter, restraint protection, overheat protection, low-voltage protection, etc. ? brake method switching circuit (free-run or reverse torque) ? 5v regulator output ? power save function specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max 30 v maximum output current i o max t 500ms 2.5 a pd max1 independent ic 0.9 w allowable power dissipation pd max2 mounted on a specified board* 2.1 w operating temperature topr -20 to +80 c storage temperature tstg -55 to +150 c *specified board: 114.3mm 76.1mm 1.6mm, glass epoxy board. monolithic digital ic for polygon mirror motors 3-phase brushless motor driver orderin g numbe r : EN6201b stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
lb1876 no.6201-2/12 allowable operating ranges at ta = 25 c parameter symbol conditions ratings unit power supply voltage range v cc 9.5 to 28 v 5v regulated output current i reg 0 to -20 ma ld pin voltage v ld 0 to 28 v fgs pin voltage v fgs 0 to 28 v ld pin output current i ld 0 to 15 ma fgs pin output current i fgs 0 to 10 ma electrical characteristics at ta = 25 c, v cc = vm = 24v ratings parameter symbol conditions min typ max unit i cc 1 17 22 ma current drain i cc 2 quiescent current 3.6 5.0 ma 5v regulated output output voltage vreg 4.65 5.0 5.35 v voltage fluctuation v reg 1 v cc = 9.5 to 28v 50 100 mv load fluctuation v reg 2 i o = -5 to -20ma 30 100 mv temperature coefficient v reg 3 design target value* 0 mv/ c output block v o sat1 i o = 1.0a, v o (sink) + v o (source) 2.0 2.5 v output saturation voltage v o sat2 i o = 2.0a, v o (sink) + v o (source) 2.6 3.2 v output leak current i o leak 100 a v d 1 i d = -1.0a 1.2 1.5 v lower side diode forward voltage v d 2 i d = -2.0a 1.5 1.9 v hall amplifier block input bias current i hb -2 -0.5 a common mode input voltage range v icm 0 v reg -2.0 v hall input sensitivity v in (ha) 80 mvp-p hysteresis width v in (ha) 15 24 42 mv input voltage l h v slh 12 mv input voltage h l v shl -12 mv fg/schmitt block input bias current i b (fgs) -2 -0.5 a common mode input voltage range v icm (fgs) 0 v reg -2.0 v input sensitivity v in (fgs) 80 mvp-p hysteresis width v in (fgs) 15 24 42 mv input voltage l h v slh (fgs) 12 mv input voltage h l v shl (fgs) -12 mv pwm oscillator output high level voltage v oh (pwm) 2.5 2.8 3.1 v output low level voltage v ol (pwm) 1.2 1.5 1.8 v external capacitor charge current i chg v pwm = 2v -125 -95 -75 a oscillator frequency f(pwm) c = 3000pf 22 khz amplitude v(pwm) 1.05 1.27 1.50 vp-p fgs output output saturation voltage v ol (fgs) i fgs = 7ma 0.15 0.5 v output leak current i l (fgs) 10 a csd oscillator output high level voltage v oh (csd) 2.65 3.0 3.3 v output low level voltage v ol csd) 0.75 0.9 1.1 v amplitude v(csd) 1.75 2.1 2.3 vp-p external capacitor charge current i chg 1 -13.5 -9 -5.5 a external capacitor discharge current i chg 2 5.5 9 13.5 a oscillator frequency f(csd) c = 0.068 f 30 hz *design target value, do not measurement. continued on next page.
lb1876 no.6201-3/12 continued from preceding page. ratings parameter symbol conditions min typ max unit phase comparator output output high level voltage v pdh i oh = -100 a v reg -0.2 v reg -0.1 v output low level voltage v pdl i oh = 100 a 0.2 0.3 v output source current i pd + v pd = v reg /2 -0.5 ma output sink current i pd ? v pd = v reg /2 1.5 ma phase lock detector output output saturation voltage v ol (ld) i ld = 10ma 0.15 0.5 v output leak current i l (ld) v o = v cc 10 a error amplifier input offset voltage v io (er) design target value* -10 +10 mv input bias current i b (er) -1 +1 a output high level voltage v oh (er) i oh = -500 a v reg -1.2 v reg -0.9 v output low level voltage v ol (er) i ol = 500 a 0.9 1.2 v dc bias level v b (er) -5% v reg /2 +5% v current limiter g df 1 in phase lock mode 0.4 0.5 0.6 times drive gain g df 2 in unlock mode 0.8 1.0 1.2 times limiter voltage v rf v cc - vm 0.45 0.5 0.55 v thermal shutdown operation operating temperature tsd design target value* (junction temperature) 150 180 c hysteresis width tsd design target value* (junction temperature) 40 c low voltage protection operating voltage v sd 8.1 8.5 8.9 v hysteresis v sd 0.2 0.35 0.5 v cld circuit external capacitor charge current i cld -6 -4.3 -3 v operating voltage v h (cld 3.25 3.5 3.75 v clk pin external input frequency f i (ckin) 0.1 10 khz high level input voltage v ih (ckin) 3.5 v reg v low level input voltage v il (ckin) 0 1.5 v input open voltage v io (ckin) v reg -0.5 v reg v hysteresis width v is (ckin) 0.35 0.5 0.65 v high level input current i ih (ckin) v ckin = v reg -10 0 +10 a low level input current i il (ckin) v ckin = 0v -280 -210 a s/s pin high level input voltage v ih (ss) 3.5 v reg v low level input voltage v il (ss) 0 1.5 v input open voltage v io (ss) v reg -0.5 v reg v hysteresis width v is (ss) 0.35 0.5 0.65 v high level input current i ih (ss) v s/s = v reg -10 0 +10 a low level input current i il (ss) v s/s = 0v -280 -210 a ldsel pin high level input voltage v ih (ld sel ) 3.5 v reg v low level input voltage v il (ld sel ) 0 1.5 v input open voltage v io (ld sel ) v reg -0.5 v reg v high level input current i ih (ld sel ) v ldsel = v reg -10 0 +10 a low level input current i il (ld sel ) v ldsel = 0v -280 -210 a brsel pin high level input voltage v ih (br sel ) 3.5 v reg v low level input voltage v il (br sel ) 0 1.5 v input open voltage v io (br sel ) v reg -0.5 v reg v high level input current i ih (br sel ) v brsel = v reg -10 0 +10 a low level input current i il (br sel ) v brsel = 0v -280 -210 a *design target value, do not measurement.
lb1876 no.6201-4/12 package dimensions unit : mm (typ) 3235a pin assignment 36 35 34 33 32 31 30 29 28 fr 27 26 25 24 23 22 21 20 19 1 out2 2 out1 3 nc 4 in3 + 5 in3 ? 6 7 8 9 in2 + in2 ? in1 + in1 ? fr 10 fgin + 11 fgin ? 12 gnd1 13 gnd2 14 pwm 15 16 17 18 fc fgfil csd ph lb1876 out3 nc gnd3 brsel ldsel vreg v cc vm2 vm1 clk s/s ld fgs cld pd ei eo toc frame frame top view 3-phase logic truth table in1 in2 in3 out1 out2 out3 h l h l h m h l l l m h h h l m l h l h l h l m l h h h m l l l h m h l in = "h" indicates the in + > in ? condition. sanyo : hsop36(375mil) (6.2) 36 1 0.8 17.8 2.7 0.3 (4.9) 10.5 0.65 0.25 (0.5) 7.9 (2.25) 2.45max 0.1 2.0 -20 0 20 40 60 80 100 pd max -- ta 0.4 0 0.8 0.9 1.2 1.6 2.0 2.1 2.4 1.18 ambient temperature, ta -- c allowable power dissipation, pd max -- w independent ic with specified board: 114.3 76.1 1.6mm 3 glass epoxy board.
lb1876 no.6201-5/12 block diagram out2 out1 in3 + in3 ? in2 + in2 ? in1 + in1 ? fgin + fgin ? gnd1 gnd2 pwm fc fgfil csd ph out3 gnd3 brsel ldsel vreg v cc vm2 vm1 clk s/s ld fgs cld pd ei eo toc fg filter ld vreg vreg ldsel pll clk tsd vreg vreg cont amp comp peak hold curr lim driver hall logic count logic sd osc brsel hall hys amp pwm osc s/s rf v cc vreg
lb1876 no.6201-6/12 pin function pin no. pin name function equivalent curcuit 2 1 36 out1 out2 out3 motor drive output pins. pwm controls duty cycle ratio by lower transistors. connect schottky diodes be tween the outputs and v cc . 34 gnd3 output block ground. 28 29 vm1 vm2 output block power supply and output current detection. vm1 and vm2 are short-circuited and used. connect low-resistance resistors rf between these pins and v cc . the output current is limited to the current value set by i out = v ref /rf. 1 2 36 34 28 vm1 29 vm2 v cc 300 3 35 nc nc since these are not connected internally, they can be used for wiring. 8 9 6 7 4 5 in1 + in1 ? in2 + in2 ? in3 + in3 ? hall device input pins. these inputs return a high level when in + > in ? and a low level when in ? > in + . a hall signal amplitude of at least 100mvp-p (differential) is desirable. insert a capacitor between in + and in ? if noise on the hall signal is a problem. 5 7 9 vreg 300 300 4 6 8 10 11 fgin + fgin ? fg comparator input pins. if noise on the fg signal is a problem, insert either a capacitor or a filter consisting of a capacitor and a resistor. 11 vreg 300 300 10 12 gnd1 control circuit block ground. 13 gnd2 sub-ground. 14 pwm pwm oscillation frequency setting pin. connect a capacitor between this pin and ground. a capacitance of 1800pf for c sets the frequency to approximately 37khz. 14 vreg 200 2k 15 fc current control circuit frequency characteristics compensation pin. insert a capacitor (on t he order of 0.01 to 0.1 f) between this pin and ground. the output duty is determined by the ratio of the voltage on this pin and the pwm oscillator waveform. 15 vreg 300 continued on next page.
lb1876 no.6201-7/12 continued from preceding page. pin no. pin name function equivalent curcuit 16 fgfil fg filter pin. if noise on the fg signal is a problem, insert a capacitor (under about 2200pf) between this pin and ground. 16 vreg 17 csd restraint protection circuit operating time setting pin/reset pulse setting pin. a protection operating time of about 8 seconds can be set by connecting a capacitor (about 0.068 f) between this pin and ground. if the protection circuit is not used, connect a capacitor and resistor (about 4700pf, 220k ) in parallel between this pin and ground. 17 vreg 300 18 ph rf waveform smoothing pin. if noise on the rf signal is a problem, insert a capacitor between this pin and ground. 18 vreg 500 19 toc torque specifying input pin. normally, this pin is connected to the eo pin. when the toc voltage falls, the on duty of the lower side transistor increases. 19 vreg 300 20 eo error amplifier output pin. 20 vreg 40k 21 ei error amplifier input pin. 21 vreg 300 continued on next page.
lb1876 no.6201-8/12 continued from preceding page. pin no. pin name function equivalent curcuit 22 pd phase comparator output pin. the phase error is converted to a pulse duty and output from this pin. 22 vreg 300 23 cld phase lock signal mask time setting pin. a mask time of about 90ms can be set by inserting a capacitor (about 0.1 f) between this pin and ground. leave this pin open if there is no need to mask. 23 vreg 300 24 fgs fg schmitt output pin. open collector output. 24 vreg 25 ld phase lock detection output pin. open collector output. turns on (goes low) when phase lock is detected. 25 vreg 26 s/s start/stop control pin. low: 0 to 1.5v high: 3.5v to vreg hysteresis: about 0.5v apply a low level to start; this pin goes high when open. 26 vreg 22k 2k 27 clk clock input pin. low: 0 to 1.5v high: 3.5v to vreg hysteresis: about 0.5 v f clk = 10khz maximum if there is noise on the clock signal, remove that noise with a capacitor. 27 vreg 22k 2k 30 v cc power supply pin insert a capacitor between this pin and ground to prevent noise from entering the ic. (use a value of 20 or 30 f or higher.) continued on next page.
lb1876 no.6201-9/12 continued from preceding page. pin no. pin name function equivalent curcuit 31 vreg stabilized power supply output (5v output) pin. insert a capacitor between this pin and ground for stabilization. (about 0.1 f.) 31 v cc 32 ldsel phase lock signal mask switching pin. low: 0 to 1.5v high: 3.5v to vreg when open, this pin goes to the high level. when low, transient unlock signals (short high-level periods on the ld output) are masked, and when high, transient lock signals (short low-level periods on the ld output) are masked. 32 vreg 30k 2k 33 brsel braking control pin. low: 0 to 1.5v high: 3.5v to vreg when open, this pin goes to the high level. when low, reverse torque control is applied and when high, the circuit operates in free-running mode. an external schottky barrier diode is required on the low side output when reverse torque control is applied. 33 vreg 30k 2k ? frame the frame pin is connected in ternally to the metal frame at the base of the ic. electrically, both the frame pin and the metal frame are left open. to improve thermal dissipation, provide a corresponding land on the pcb and solder the frame pin to that land.
lb1876 no.6201-10/12 lb1876 overview 1. speed control circuit this ic provides high-precision, low-jitter, and stable mo tor rotation since it adopts a pll speed control technique. this pll circuit compares the phases of the edges on the cl k signal (falling edges) and the fg signal (falling edges on the fgin + , fgs output) and controls the speed using that error output. the fg servo frequency during control operation is the same as the clock frequency. f fg (servo) = f clk 2. output drive circuit to reduce power loss in the output, this ic adopts a di rect pwm drive technique. the output transistors are always saturated when on, and the motor drive power is controlled by changing the output on duty. since the lower side transistor is used for the output pwm switching, schottky diodes must be inserted between the outputs and v cc . (this is because if the diodes used do not have a short reverse recovery time, instantaneous through cu rrents will flow when the lower side transistor turns on.) the diodes between the outputs and ground are built in. however, if problems (such as waveform disruption during lower side kickback) occur for large output currents, attach external rectifying diodes or schottky diodes. if reverse control mode is selected for braking and problems such as incorrect operation or exce ss heat generation due to the reverse recovery time of the lower side diode causes a problem, add an external schottky diode. 3. current control circuit the current control circuit controls the current (limits the peak current) to the current determined by i = v rf /rf (v rf = 0.5v typ., rf: current detection resistor). the limiting oper ation consists of reducing the output on duty to suppress the current. the current control circuit detects the diode reverse recovery current due to the pwm oper ation, and has an operating delay (about 3 s) to prevent incorrect current limiting operation. if the motor coils have a relatively low resistance, or relatively low inductance, the changes in current flow at startup (the stat e where the motor presents no back electromotive force) will be rapid. as a result, the current li miter may operate at currents in excess of the set current due to this delay. in such cases, the current limit value must be set so as to take the current increase due to the delay into account. 4. power saving circuit this ic goes to the power saving state, which reduces power consumption, in the stopped state. power is reduced in the power saving state by cutting the bias current to most of the circuit blocks in the ic. however, the 5 v regulator circuit does operate and provide its output in the power saving state. 5. reference clock the externally input clock signal must be free of chattering and other noise. the input circuit does have hysteresis, but if problems occur, the clock signal must be input through a capacitor or other noise reduction circuit. if the ic is set to the start state with no reference clock inpu t, and if the constraint protection circuit is operated, after the motor rotates a certain amount, th e drive will be turned off. however, if the constraint protection circuit is not operated, and furthermore, if reverse control mode is selected duri ng braking, the motor will run backwards at increasing speed. a workaround will be required in this case. (this problem occurs because the constraint protection circuit oscillator signal is used for clock cutoff protection.) 6. pwm frequency the pwm frequency is determined by the ca pacitor c (f) connected to the pwm pin. f pwm 1/(15000 c) if an 1800pf capacitor is used, the frequency will be about 37khz. if the pwm frequency is too low, the motor will emit audible switching noise, and if it is too high, the power loss will increase. a frequency in the range 15 to 50khz is desirable. the capacitor ground must be connected as close as possible to the ic control block ground (the gnd1 pin) to minimize the influence of the output on this circuit. 7. hall sensor input signals input signals with amplitudes greater than the input circuit hysteresis (42mv maximum) must be provided to the hall inputs. input amplitudes of over 100mv are desirable to minimize the influence of noise. if the output waveform is disturbed by noise (at phase switching), insert capacitors across the input to prevent this.
lb1876 no.6201-11/12 8. fg input signal normally, one of the hall sensor signals is input as an fg signal. if noise on the fg input is a problem, insert either a capacitor or a filter consisting of a capacitor and a resistor. although it is possible to exclude noise from the fg signal by inserting a capacitor between the fgfil pin and ground, if this pin's waveform is smoothed excessively, the circuit may not be able to operate normally. therefore, if a capacitor is used here, its value must be held to under 2200pf. if the position of the capacitor's ground lead is inappropriate, problems due to noise may become more likely to occur. select the position carefully. 9. constraint protection circuit this ic includes a built-in constraint protection circuit to pr otect the ic and the motor during motor constraint. in the start state, when the ld output is high for a fixed period (t he unlocked state), the lower si de transistor turns off. the time is set by the capacitor connected to the csd pin. set time (seconds) 120 c ( f) if a 0.068 f capacitor is used, the protection time will be about 8 seconds. the set time must have a value that provides an adequate margin relative to the motor start time. the protection circuit does not operate during braking implemented by switching the clock frequency. either switch to the stop stat e or turn off the power and re start to clear the constraint protection state. since the csd pin also functions as the initial reset pulse gene ration pin, if connected to ground the logic circuits will be reset and speed control operation will not be possible. ther efore, if constraint protectio n is not used, connect csd to ground through a resistor of about 220k and a capacitor of about 4700pf in parallel. 10. phase lock signal (1) phase lock range since this ic does not have a counter in the speed control system, the speed error range in the phase locked state cannot be determined solely by the ic's characteristics. (this is because of the influence of the acceleration of the changes in the fg frequency.) if it is necessary to stipulate this for the motor, it will be necessary to measure this with the actual motor. since it is easier for sp eed errors to occur in the state where the fg acceleration is large, the largest speed errors are thought to occur during lock pull-in at startup and when unlo cked due to clock frequency switching. (2) phase lock signal mask function when the ldsel pin is set high or left open, transient lo ck signals (short low-level periods on the ld output) is masked. this function masks short low-level periods due to hunting during pull-in and allows a stable lock signal to be output. however, the lock signal is delayed by amount of masking time. when the ldsel pin is set low, transient unlock signals (short high-level periods on the ld output) is masked. this function prevents short period high-level signals from being output. the mask time is set with the capacitor connected between the cld pin and ground. mask time (seconds) 0.9 c ( f) a mask time of about 90ms can be set by using a capacitor of about 0.1f. if complete masking is required, the mask time must be set large enough to provide ample margin. if masking is not required, leave the cld pin open. 11. power supply stabilization since this ic provides a large output current and adopts a switching drive t echnique, it can easily disrupt the power supply line voltage. therefore, capacitors with ample capacitance must be inserted between the v cc pins and ground. if reverse control mode is selected durin g braking, the circuit will return current to the power supply. this means that the power supply lines are even more susceptible to disruption. since the power supply is most easily influenced during lock pull-in at high motor speeds, this case requires particul ar care. select capacitor values that are fully adequate for this case. if diodes are inserted in the power s upply lines to prevent damage if the power supply is connected with reverse polarity, the power supply voltage will be even more susceptible to disruption, and even larger capacitors must be used. 12. vreg stabilization insert a capacitor of at least 0.1 f to stabilize vreg, which is the control ci rcuit power supply. the capacitor ground must be connected as close as possible to the ic control block ground (the gnd1 pin). 13. error amplifier circuit components locate the error amplifier components as close to the ic as possible to minimize the influence of noise on this circuit. locate this circuit as far from the motor as possible.
lb1876 ps no.6201-12/12 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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